1. Field of the Invention
The present invention relates to phase locked loop systems, and more particularly, to automatically adjusting parameters within a phase locked loop system to enhance performance.
2. Background of the Invention
In the last several years distributed computing and communications systems that rely on or provide high speed data communications have become nearly ubiquitous. Such systems may include, but are not limited to, broadband communication systems using cable modems, satellite communication systems, fiber to the home (FTTH) communications networks, and board-to-board interconnections in a myriad of electronic devices.
In many of these systems, a remote electronic device must replicate a signal provided by another electronic device. One of the more common reasons an electronic device replicates a signal provided by another device is to provide clock synchronization between two or more electronic devices. There are many reasons why remotely distributed devices may need to have their clocks synchronized. In particular, in a digital communication system the receiving device must be properly synched to a sending device to enable the efficient processing and interpretation of an incoming data stream.
Phase locked loop (PLL) systems are typically used to facilitate synchronization of remotely located devices. A PLL system is a feedback system in which the feedback signal is used to lock the output frequency and phase to the frequency and phase of an input signal. FIG. 1 illustrates the basic architecture of a PLL system. As depicted in FIG. 1 the basic components include phase detector 110, loop filter 120 and voltage controlled oscillator 130. Phase locked loops can be analog or digital with the majority being composed of both analog and digital components.
In the basic PLL system illustrated in FIG. 1, input signal V(t) 140 is applied to one input of phase detector 110 while the output signal X(t) 170 is applied to the other input of phase detector 110. The output of phase detector 110, E(t) 150, is a function of the phase difference between V(t) 140 and X(t) 170. Loop filter 120 filters out undesirable components from E(t) 150 and provides further control over the loop""s frequency response. Thus, loop filter 120 produces an output signal, Y(t) 160, that is primarily a function of the phase difference between V(t) 140 and X(t) 170.
Voltage controlled oscillator 130 is an oscillator whose output frequency is a linear function of its input voltage over some range of input voltages. A positive voltage will cause the frequency of the output signal of voltage controlled oscillator 130 to be greater than its uncontrolled value, while a negative voltage will cause it to be less. When an input signal has a frequency and phase within a certain range, known as the capture range, the PLL system will go through a series of cycles in which the difference between V(t) 140 and X(t) 170 becomes smaller and smaller until the signals are substantially the same. The system is said to be xe2x80x9clockedxe2x80x9d,when the frequency and the phase of V(t) 140 and X(t) 170 are substantially the same. If the input signal has a frequency and phase outside the capture range, the system will not achieve lock and V(t) 140 and X(t) 170 may diverge, instead of converging.
Acquisition rate is a key performance characteristic of a PLL system. Acquisition rate refers to the rate at which a PLL system achieves lock, that is, to generate an output signal, such as X(t) 170 that has the same phase and frequency as an input signal, such as V(t) 140. Acquisition rate is a function of a variety of factors. Among these factors are the quality of the circuit components, the range of the input signal frequency and phase, and the characteristics of the input signal (e.g., digital or analog, noise levels, etc.).
As communication speeds have increased, there has been a need to improve acquisition rates. There are two basic situations when a PLL system needs to acquire lock to an input signal. These situations are upon system start-up and following the loss of lock during operation. When a PLL system is acquiring lock upon system start-up, the throughput degradation attributable to a slow acquisition rate may not be perceptible. However, when a system is operating and lock is lost, having a slow acquisition rate may significantly degrade performance. While start-up acquisition, by definition, only occurs once, re-acquisition during operation may occur many times. Because the re-acquisition occurs while data is likely being transmitted, data may be lost. The longer the re-acquisition, the more data is lost and the greater the time needed to recover the data. Thus, minimizing the acquisition time plays an important role in maximizing system throughput, particularly in environments where the signal or PLL lock may be lost frequently.
The damping factor is another key performance characteristics of a PLL system. The damping factor refers to the PLL system response to a change in the characteristics of the input signal. In particular, when there is a change in the input signal phase, the damping factor will determine the PLL system gain. If this gain is too large the PLL system will lose lock. Additionally, the damping factor determines how quickly ringing (i.e., a decaying sinusoidal variation in the output voltage of a loop filter) will cease following a change in the input signal phase. The sinusoidal variations will introduce undesirable jitter into the replicated signal. Thus, having a fast decay rate is often desirable.
The loop bandwidth is another key performance characteristics of a PLL system. The loop bandwidth refers to the range of operating frequencies where a PLL system has a predictable and desirable response. During initial signal acquisition, the loop bandwidth should be such that the frequency of the input signal lies within the loop bandwidth. Once signal acquisition has occurred, the loop bandwidth should include the frequency of the input signal, but ideally be as small as possible to reduce unwanted noise.
One type of communications system where PLL systems are commonly used is a cable modem-based broadband communications system. Within a cable modem-based broadband communication system the two principle devices are cable modems and cable modem termination systems. In a broadband communications network that uses cable modems, typically many cable modems are connected to a single cable modem termination system. Cable modems are located at customer premises and typically connected to personal computers through an Ethernet connection. Cable modem termination systems are typically located within a service provider""s network center, often known as a headend location. Cable modem termination systems exchange data with multiple cable modems at high speeds. Importantly, cable modem termination systems transmit clock signals to cable modems for synchronization that is critical to ensuring efficient operation and high throughput.
Cable modem networks transmit data at high speeds that require optimization of circuitry and procedures. In particular, in a cable modem network in the downstream direction (from the network to a user""s computer) network speeds can reach 40 Mbpsxe2x80x94an aggregate amount of bandwidth that is shared by multiple users. In some systems network speeds can reach speeds approaching 100 Mbs. Typically, the downstream speed per user is on the order of 1 to 3 Mbps. Thus, if acquisition of a clocking signal delays transmission of data by only a tenth of second, the cable modem termination system will be prevented from sending 4.0 Mb of data. Depending on how often clock synchronization is lost, this could result in a performance degradation of up to 10%. This is unlikely because clock synchronization is not typically lost once a second. Nonetheless, as service providers receive greater and greater pressure from consumers for higher speed transmission rates, it is critical for circuitry and procedures to be optimized.
Similarly, once an input signal has been acquired, being able to control the damping factor and loop bandwidth dynamically can enhance performance. Within a digital PLL system, for example, the damping factor and loop bandwidth will change as the input signal rate changes. Thus, to ensure that the desired damping factor and loop bandwidth is achieved, dynamic adjustments must be made. By controlling the damping factor and loop bandwidth, noise contained within the output signal of the PLL system and the probability of losing signal lock can be reduced.
When dealing with systems that are transmitting data at megabit speeds, such as current broadband cable modem communications systems, minimizing acquisition time, reducing noise and avoiding lose of signal is critical. While there currently are approaches to aid a PLL system to achieve lock and to reduce acquisition rates, these approaches are either relatively slow given current communication speeds or require complex circuitry. Likewise, adjusting the damping factor and loop bandwidth dynamically requires the use of an external processor that is not always cost effective.
The invention is directed to a signal recovery system and methods to quickly acquire signal lock and maintain consistent performance of the signal recovery system for different input rates of an input signal. The system includes a phase locked loop system and a parameter controller. The method includes monitoring an input signal, determining the signal input rate of the input signal, providing shift factors to a loop filter contained within the signal recovery system, and adjusting the PLL system performance based on the shift factors. The performance factors that can be modified include the acquisition rate, loop bandwidth, and damping factor of the PLL system within the signal recovery system.
In one embodiment of the invention, the invention is implemented within a cable modem. In this embodiment, the invention is used to enhance the ability of the cable modem to achieve and sustain synchronization to a clock signal received from a cable modem termination system. In this embodiment, a cable modem termination system transmits a clock signal to a cable modem, pursuant to requirements in DOCSIS 2.0. DOCSIS 2.0 is an industry standard describing the protocols required for use between cable modems and cable modem termination systems. The cable modem must lock onto the clock signal and replicate it locally for efficient operation. The invention is used to achieve signal lock quickly, and to enhance the ability of the cable modem to sustain signal lock.
Use of the invention provides three principal benefits. First, use of the invention provides a significant improvement in the time it takes for a remote electronic device to lock onto a signal from another electronic device. Second, use of the invention increases the likelihood that signal lock will not be lost when there are changes in the input signal phase or frequency. Third, use of the invention enables the loop bandwidth to be smaller and the damping factor to be more stable than if the invention was not used, thereby reducing unwanted noise and jitter in the output signal of the signal recovery system.
Collectively, the benefits of the invention improve the operational efficiency and enable data throughput rates to be higher than they would be without the use of the invention.
Further embodiments, features, and advantages of the invention, as well as the structure and operation of the various embodiments of the invention are described in detail below with reference to accompanying drawings.